As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, device fabrication technology is migrating from aluminum metal interconnects to copper interconnects and from traditional silicon-dioxide-based dielectrics to low-k dielectrics, such as organo-silicate glass (OSG). Semiconductor fabrication processes that work with copper interconnects and newer low-k dielectrics are still being developed and optimized. As compared to the traditional subtractive plasma dry etching of aluminum, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a damascene process, the IMD (intrametal dielectric) is formed first. The IMD is then patterned and etched to form a trench for the interconnect line. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, vias are etched into the ILD (interlevel dielectric) 12 for connection to lower interconnect levels and trenches are etched into the IMD 14. The barrier layer 16 and a copper seed layer are then deposited over open via/trench structures. The barrier layer 16 is typically tantalum nitride or some other binary transition metal nitride and the thin Cu seed layer is deposited using physical vapor deposition. A copper layer is then electrochemically deposited onto the seed layer that covers the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper over the IMD 14, leaving copper interconnect lines 18 and vias 20 as shown in FIG. 1. A metal etch is thereby avoided.
Typically, several copper interconnect layers are successively formed. After one metal interconnect layer is formed, an etchstop layer is deposited thereover and the next levels' ILD and IMD are formed. The etchstop layer prevents Cu diffusion from the metal lines into the overlying oxide-based dielectric and protects the Cu from subsequent via/trench etches used to form the next level of interconnect.